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BCH (15,11,1) algorithm With VHDL

立即報名
  • 14 名學生
  • 更新於 7/2022
3.9
(06 個評分)
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  • 透過本站連結購買Udemy課程,本站將獲得推廣佣金,有助未來提供更多實用進修課程資訊給讀者。

課程資料

報名日期*
全年招生
課程級別
學習模式
修業期
0 小時 30 分鐘
教學語言
英語
授課導師
Amr Ahmed
評分
3.9
(06 個評分)
*提示: 以上時間表僅供參考,以機構網站為準。

課程簡介

BCH (15,11,1) algorithm With VHDL

VHDL Code of BCH (15,11,1) algorithm


  • The course contains some lectures that explain in detail the Bose–Chaudhuri–Hocquenghem codes (15,11,1) algorithm used for error detection and correction. the number 15 is referring to the total transmitted message bit size, 11 is the information bit size, and 1 is the number of errors that can be detected and corrected.

  • the course contains a VHDL code for the algorithm that is attached to the lectures that you can download and use it.

  • This course targets the VHDL code and the FPGA implementation of this algorithm. it will be helpful for the undergraduate engineering students and the postgraduate also.

  • the VHDL codes are not easy to be valid on the websites so it is difficult to find the VHDL code for a certain project that works correctly but in this course, the full VHDL code will be available with its test bench so you can download and adjust it as you want.

  • You will learn by doing real VHDL programming. All the code and syntax are attached. After you adjust the existing code or you create your own, you will run simulations to verify it. If you are interested to run your code on real hardware (not required, but much more fun), we recommend Altera or Xilinx boards.

課程章節

  • 1 個章節
  • 5 堂課
  • 第 1 章 Introduction

課程內容

  • Define the coding theory, Define the Bose–Chaudhuri–Hocquenghem (BCH) codes, Define the types of BCH codes, Explain the BCH (15,11,1) encoder with VHDL, Explain the BCH (15,11,1) decoder with VHDL

此課程所涵蓋的技能


評價

  • A
    Ahmed
    5.0

    very good course

  • S
    Shashank Doharey
    5.0

    This is a good start for a beginner like me to implement actual physical hardware realization of one of those uncountable information theory & coding related VLSI projects on a FPGA hardware for practice.

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