Master FPGA design with VHDL : Alarm Clock

Design and Build a Functional Alarm Clock Using FPGA and VHDL: From Concept to Hardware Implementation

This course is designed to immerse you in the world of hardware engineering. The course will guide you through the process of converting requirements and needs into practical and efficient designs. You will explore the basic concepts of digital circuits and VHDL coding rules and syntax. Furthermore, the course will cover the use of constraints files, synthesis and simulation of HDL designs, enabling you to verify the correctness of your circuits before physical implementation. By the end of the course, you will have a comprehensive skill set to design, implement, and test digital systems.

To achieve all of the above, we will design in VHDL an Alarm Clock on FPGA. One external 4 digits 7-segments display will be connected to the FPGA via wires to display the time in HH:MM format. This is ideal to learn about FPGA PMODs and IO pins. The design will allow the user thanks to switches to set either the current time or the alarm. In "SET" mode, the configuration of the clock and alarm will be done by pressing push buttons to either increment minutes or hours. When the current time reaches the configured alarm set by user, a buzzer connected to FPGA will buzz for one minute.

By the end of the course, students will have the practical skills and experience required to design, implement, and verify their own fully functional digital alarm clock system on an FPGA, providing a solid foundation for further FPGA and digital design projects.