Udemy

VSD - SoC Design of the PicoRV32 RISCV micro-processor

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  • 685 Students
  • Updated 6/2018
3.9
(65 Ratings)
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Course Information

Registration period
Year-round Recruitment
Course Level
Study Mode
Duration
4 Hour(s) 6 Minute(s)
Language
English
Rating
3.9
(65 Ratings)

Course Overview

VSD - SoC Design of the PicoRV32 RISCV micro-processor

Freedom to build micro-processors

This webinar was conducted on 2nd June 2018

After successful webinar on Making of Raven Chip, this time we take the chip forward and implement using end-to-end opensource EDA tools, and all on efabless cloud. What does this mean to us? It means, you can start innovating on a design, build RTL and do synth/PD/LVS/DRC all using opensource EDA framework and not pay a single penny for license.

The big question How is this possible? Thereby, I welcome you all to my next (follow-up) webinar with Tim Edwards and Mohamed Kassem

About instructors -

Tim Edwards


Tim Edwards has been doing analog VLSI design and collecting and developing open-source EDA
tools for over 25 years. He has worked for the Johns Hopkins Applied Physics Lab, startups MultiGiG (bought by Analog Devices) and most recently, eFabless.


Mohamed Kassem


Mohamed Kassem is the cofounder and CTO of eFabless corporation. Prior to
launching eFabless in 2014, Mohamed held several technical and global
leadership positions within TI's Wireless Business Unit. He
joined TI in 2000 at the beginning of the digital telephony revolution
fueled by the unprecedented integration of major phone functions on a
single SoC. He led the first development of 45nm, 28nm analog & mixed-signal IP functions for wireless applications processors. Mohamed holds a masters degree in electrical engineering from the University of Waterloo, Ontario, Canada.


Course Content

  • 8 section(s)
  • 28 lecture(s)
  • Section 1 Introduction
  • Section 2 efabless interactive tutorial
  • Section 3 CloudV interactive tutorial
  • Section 4 Synthesis flow interactive tutorial
  • Section 5 LVS & DRC
  • Section 6 Full chip integration in open-galaxy
  • Section 7 Signal routing
  • Section 8 Challenge & Conclusion

What You’ll Learn

  • Run a full physical design flow from RTL design to GDSII, making it ready for tape-out., For freshers, this course will make them industry ready and might increase their chances of getting placed or work for tier-1 company, For experienced VLSI Physical design professionals, this will give a bigger picture of SoC physical design, which is appplication specific, For senior non-VLSI engineers, this course will help them understand the whole flow, with pictures, labs and visualization

Reviews

  • C
    Chitransh Kulshreshtha
    2.0

    This is a webinar and not a course. The platform which is used is not online anymore. The title says Raven chip and shows only a small sub-section in the end. Any free video on the web will show these details.

  • D
    Daniel Limbrick
    2.0

    Platforms used (e.g., CloudV, OpenGalaxy) are no longer available

  • L
    Liam Dillon
    3.5

    Recording of a webinare...

  • M
    Mehmet Sait Eroğlu
    4.0

    I think these webinars should have been given by Kunal. Tim Edwards is an expert but not a good explainer. He skips the details and Kunal is very good at details. So that, by just clicking to buttons in Qflow respectively, students or junior vlsi enginners do not understand the details in order to use those in commercial tools. Thanks.

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