Course Information
Registration period
Year-round Recruitment
Course Level
Study Mode
Duration
4 Hour(s) 44 Minute(s)
Language
English
Taught by
Prof. Dr. Academic Educator
Rating
Course Overview
State Machines and VHDL programming
In this course, the students will get information about the state machines and VHDL implementation of state machines. We first give information about the Mealy and Moore state machines and solve some problems about the state machine characterization of real life and mathematical problems. Then, VHDL programming of state machines is taught.
Course Content
- 1 section(s)
- 18 lecture(s)
- Section 1 Introduction to State Machines and VHDL Implementation of State Machines
What You’ll Learn
- State Machines, VHDL Implementation of State Machines, Timed State Machines, VHDL Implementation of Timed State Machines
Skills covered in this course
Reviews
-
AAleksandar Dobric
Cons: strange accent (not fluid english). Pros: Very well visually explained with a lot of quality visual content. As I always say: 1 picture = 1000 words
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TTommy Sullivan
The instructors accent and his strange inflections made it very hard for me to understand him. I hate to say that in a review but, it's how I felt. The material was fine although, I think it could have gone a little faster.
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JJohn F Brune
audio is unintelligible, I can deal with heavy accents but this audio is not usable.
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AAT Shahin
Excellent! Highly recommend to anyone who wants to learn and design state machines in VHDL.
