Course Information
Course Overview
FPGA Design approach with System Generator of MATLAB/Simulink & HDL Coder, Course introduced the Complete Design Flow
This Course will let you know about "How to Design FPGA based Signal Processing Projects on MATLAB/Simulink".
This course is on Designing FPGA based Signal Processing Projects with MATLAB/Simulink and FPGA Design Tool (Xilinx VIVADO/ISE), we are going to use Xilinx System Generator (interface between MATLAB/Simulink and VIVADO/ISE) and HDL Coder. From this two tools we can design our projects on traditional MATLAB/Sumilink design flow; using Blocks and integrating blocks in Simulink or using MATLAB codes and finally converting this two types of design in to HDL or into Bitstream so we can program FPGA from MATLAB/Simulink or VIVADO/ISE.
We have session on FIR,IIR, LMS Filter Design and OFDM Modulation algorithm implementation on FPGA.
MATLAB & Simulink are the best tools for Signal Processing Projects, while FPGA are best hardware platform for such type of Signal Processing Projects cause of it's flexibility and processing capabilities.
Course Content
- 7 section(s)
- 17 lecture(s)
- Section 1 Section_1 Installation of Matlab/Simulink and VIVADO/ISE
- Section 2 Section_2 Introduction to HDL Coder and System Generator
- Section 3 Section_3 Project with System Generator
- Section 4 Section_4 Advance Design with HDL Coder
- Section 5 Section_5 Advanced Design with System Generator
- Section 6 Section_6 Zynq Development with System Generator & VIVADO
- Section 7 Bonus Lecture + Vitis Model Composer(VMC)
What You’ll Learn
- FPGA Development with Matlab and Simulink Tool., Creating Projects with System Generator and HDL coder, Implementing FIR and IIR Filter on FPGA from System Generator, Implementation of OFDM modulation on FPGA, Zynq FPGA Design with Matlab/Simulink (System Generator), LMS filter design with HDL coder from Matlab
Skills covered in this course
Reviews
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RRichard Ormheser
cannot understand
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HHacer Danacı
Yeni şeyler öğrendim
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SSohail Ahmed
The words spoken by the presenter could have been better scripted. He should have been better prepared. The course does not take any project to culmination. All projects are unfinished. It would have been great to have at least project from start to finish and implemented on an FPGA board. Overall, not much learning value in this course.
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LLAURIS STEPHANE TAGUETIEU
Some interesting tips, but I find that the course is too general and not structured enough.