課程資料
報名日期
全年招生
課程級別
學習模式
修業期
9 小時 19 分鐘
教學語言
英語
授課導師
Scott Dickson
評分
2次瀏覽
課程簡介
From VHDL basics to sophisticated testbench coding
Twelve lectures, starting from the basics of VHDL, including the entity, architecture, and process. Explanations of the difference in sequential and concurrent VHDL. Discussions of good synchronous design methodology. Demonstrations on how to use the Altera Modelsim and Xilinx Vivado simulators. Six lab projects for hands-on experience, with the instructor showing how he would have done each lab.
課程章節
- 6 個章節
- 26 堂課
- 第 1 章 Introduction to VHDL , a first look
- 第 2 章 Concurrent and Sequential VHDL
- 第 3 章 RTL
- 第 4 章 VHDL Types
- 第 5 章 VHDL Operators
- 第 6 章 Verification
課程內容
- Practical FPGA and ASIC RTL design using VHDL
此課程所涵蓋的技能
評價
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PPatricia Maestre Esteban
The course is fine but it could be better to have some support material.
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SScooter Johnson
Professor describes all the code and rationale very clearly with a lot of examples.
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PParas Kore
The pace of the course is well matched and the instructor is explaining the course in a simple manner making it understandable to anyone watching the course video. The instructor is also very well versed with the content he is teaching us.
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CCarlos Camargo
The instructor knows the topic well and makes the material easy to understand. This is a great course to learn the material well.
