Udemy

Introduction to VHDL for FPGA and ASIC design

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  • 7,695 Students
  • Updated 8/2024
4.5
(1,428 Ratings)
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Course Information

Registration period
Year-round Recruitment
Course Level
Study Mode
Duration
9 Hour(s) 19 Minute(s)
Language
English
Taught by
Scott Dickson
Rating
4.5
(1,428 Ratings)
2 views

Course Overview

Introduction to VHDL for FPGA and ASIC design

From VHDL basics to sophisticated testbench coding

Twelve lectures, starting from the basics of VHDL, including the entity, architecture, and process.  Explanations of the difference in sequential and concurrent VHDL.  Discussions of good synchronous design methodology.  Demonstrations on how to use the Altera Modelsim and Xilinx Vivado simulators. Six lab projects for hands-on experience, with the instructor showing how he would have done each lab.

Course Content

  • 6 section(s)
  • 26 lecture(s)
  • Section 1 Introduction to VHDL , a first look
  • Section 2 Concurrent and Sequential VHDL
  • Section 3 RTL
  • Section 4 VHDL Types
  • Section 5 VHDL Operators
  • Section 6 Verification

What You’ll Learn

  • Practical FPGA and ASIC RTL design using VHDL


Reviews

  • P
    Patricia Maestre Esteban
    4.0

    The course is fine but it could be better to have some support material.

  • S
    Scooter Johnson
    4.5

    Professor describes all the code and rationale very clearly with a lot of examples.

  • P
    Paras Kore
    4.5

    The pace of the course is well matched and the instructor is explaining the course in a simple manner making it understandable to anyone watching the course video. The instructor is also very well versed with the content he is teaching us.

  • C
    Carlos Camargo
    5.0

    The instructor knows the topic well and makes the material easy to understand. This is a great course to learn the material well.

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