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Effective Verilog learning using Intel and Xilinx FPGAs

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  • 552 Students
  • Updated 10/2024
  • Certificate Available
4.3
(83 Ratings)
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Course Information

Registration period
Year-round Recruitment
Course Level
Study Mode
Duration
14 Hour(s) 2 Minute(s)
Language
English
Taught by
Muhammad Tahir Rana
Certificate
  • Available
  • *The delivery and distribution of the certificate are subject to the policies and arrangements of the course provider.
Rating
4.3
(83 Ratings)

Course Overview

Effective Verilog learning using Intel and Xilinx FPGAs

The step-by-step learners guide through Intel and Xilinx FPGAs based system development.

This course is designed to make students confident developers of Digital Systems using Verilog and AMD and  Intel FPGAs (2 different boards and FPGAs). Every aspect is discussed from different angles so that the whole concept becomes clearer. This course uses two cheap Intel FPGA development boards and a Digilent(AMD) board along with freely available software(Quartus Lite, ModelSim, Vivado). Purchasing of boards is absolutely optional. This course can be done without development boards.

Additionally, FPGAs and toolchains from other vendors are also introduced briefly.

This course takes you through:

  • Design using Verilog HDL (in the simplest possible ways)

  • Tool setup, which is the hardest part.

  • Tool automation introduces the techniques that I learned over the years.

  • Different FPGA architectures

  • Managerial side of choosing parts for development

  • Simulation makes sure whether the design is correctly made

  • And above all, I share the experience that I gained over the years.

As a word of caution: I have not updated this course for a long time. The Toolchains of both Xilinx(now AMD) and Quartus have evolved a bit. Please try to download the tools and if you don't understand the tool setup ask for your money asap without wasting time. I teach as a hobby, and teaching is one of my passions. Feel free to request, upgrades or any help. I am here for you.


Enjoy and rock and roll in your career.

Course Content

  • 9 section(s)
  • 86 lecture(s)
  • Section 1 Introductions
  • Section 2 Software Installations
  • Section 3 Introduction to Hardware Description Language(HDL)
  • Section 4 HDL Design Constructs with Examples
  • Section 5 TCL Language and Testing Automation
  • Section 6 Some Quartus options
  • Section 7 Advance Topics and UART Project
  • Section 8 Conclusion: Intel Part
  • Section 9 Additional Resources 1: Xilinx Tool chain and FPGAs

What You’ll Learn

  • Hardware Description Language ( in this case, Verilog), different design constructs, efficient development handling, TCL for Verification-Automation etc
  • Our basic target will be Intel FPGAs and Development tools. A small part regarding Xilinx FPGAs is also included.
  • The goal of this course is to train young professionals for independent development.
  • All Examples and software will be done in Windows (10) environment. Students with Windows 7 and 8 may also join the course. (Sorry Linux Guys)
  • Development board is optional. All Software used in this course is freely available. But a computer with Windows Operating system is a must.
  • We will analyze already developed codes, so that I may have time to explain codes and syntax in more detail. This step I took to shrink course duration.
  • 2 Intel FPGA based development Boards are introduced. 1 Xilinx FPGA based development Board and Xilinx tool chain is also introduced.


Reviews

  • D
    Douglas Santos Reis
    3.5

    Content is good, but the audio quality could be improved.

  • J
    Joshua Harmon
    5.0

    Awesome !!

  • R
    Rashad AbdulAzeem
    5.0

    The code and examples are explained thoroughly.

  • B
    Brian Beattie
    1.5

    In first section Audio quality could have been better. Volume much lower than intro, audio also had some drop outs. Content and presentation were good. Section 32. introduces three files without first explaining their contants, leaving it up the the student to figure out how to create them. Then later the gate level simulation fails and the ModelSim transcript includes the message "Error: Error loading design" so that I'm not sure that I created all files correctly. This apears to be a problem with the license running Quartus Prime lite 18.1. ModelSim runs fine from the command line but not from Quartus. All example files should be included in the Resources, the files were full_adder.v four_bit_adder.v, the test bed file was covered later, though I had some trouble with that because entering files by hand is error prone.

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